1. Field of the Invention
This invention relates to radio frequency (rf) sputter etch systems and more particularly to a device configured upon a semiconductor wafer or upon the sputter etch system which reduces damage associated with the sputter etch.
2. Background of the Relevant Art
The process of sputtering and sputter-etching has been studied and used for many years. More recent advances in sputter technology has led to the use of rf power systems for driving the sputter electrode. See, e.g., B. Chapman, "Glow Discharge Processes," J. Wiley and Sons, New York, N.Y., 1980, pp. 135-173. RF sputtering includes both the deposition of thin films or the removal of thin films. Depending upon whether the object is placed upon the cathode or anode, either deposition or etching of thin films can occur. RF sputtering is sometimes used for deposition or etching of insulators which cannot easily be performed using direct current (dc) techniques due to substrate and target charging. RF sputter deposition is widely used for insulators such as silicon dioxide, aluminum dioxide, and/or other oxides where the substrate temperature limits preclude other techniques. Conversely, sputter etching is often used for pattern transfer, but because sputter etching is a high-energy process, it is rarely used for patterning thick films, except where the energy requirements can be lowered using chemical reaction (RIE) techniques.
Sputter etching using rf power is sometimes used to remove surface oxides in contact areas prior to metal sputter deposition. This has been shown to be effective for making low-resistance contact between successive aluminum thin-film wiring layers on semiconductor devices. Accordingly, second metallization layers can make good electrical contact to underlying layers due to the effective removal of native oxides which naturally grow within the contact areas prior to deposition. See, e.g., Rossnagel, S., et al., "Handbook of Plasma Processing Technology," Noyes Publ., Park Ridge, N.J., 1990, pp. 154-157.
It is well recognized that rf discharges generally occur at relatively high voltage (600-1500 volts) and at high frequency (13.56 MHz). Plasma is formed near the wafer surface by breakdown of the gas within the sputter etch chamber. Electrons are repelled from the insulating layer (i.e., from the native oxide within the contact area) for most of the rf cycle, resulting in a positive time-averaged space charge. However, the cathode is usually smaller than the anode so that a high negative dc bias is developed on it with respect to the plasma. The cathode electrode and electrically connected wafer is bombarded at high energy by ions within the plasma during the negative portion of the applied voltage, and by electrons during the positive portion of the applied voltage. The resulting flow of ions and electrons during each cycle must be equal in order to preserve necessary charge neutrality. The electrons, being highly mobile, can easily provide enough charge over a small fraction of the cycle to neutralize the positive ion charge which flows during a majority of the cycle.
The bombardment of high energy ions upon the insulating layer dislodges atoms from the layer which are then accelerated by an applied electric field toward what is commonly called a "catcher plate" placed within the etch chamber. The catcher plate functions similar to an anode and preferrably has deep cavities similar to a honeycomb structure, and also should be well grounded with low-conductance, wide straps or foils to prevent self-bias.
Although plasma etching using rf sputtering techniques is well suited to provide fine-line removal of native oxides in an anisotropic fashion, there are many disadvantages associated with plasma etch as reported in Singer, P., "Evaluating Plasma Etch Damage," Semiconductor International, May, 1992, pp. 78-81. Sputter etch can cause significant damage to the active regions within a semiconductor wafer. As defined herein, "active regions" refer to areas within a semiconductor having elements which can be activated in order to perform the specified functions of the integrated circuit defined thereon. Thus, active regions include those regions having passive or active elements (capacitors, resistors, transistors, etc.) necessary to carry forward the operation of the integrated circuit. Conversely, "inactive regions" are those regions which are defined outside the active regions and do not provide direct functionality of the integrated circuit. Generally, inactive regions are formed outside the die or integrated circuit area. Inactive regions, found near the outer periphery of the wafer, are generally unsuitable for accommodating an entire die. Inactive regions are usually discarded after the die are scribed and removed from the wafer. As described in the article to Singer, plasma etch can induce damage within the active area and may cause (i) gate oxide breakdown, (ii) high reverse leakage current, (iii) low minority carrier lifetime, (iv) foreign matter contamination of the silicon surface, (v) short order crystalline damage of the silicon surface, and (vi) radiation and lattice damage contamination from resist etch residues. The damage can result in skewed current-voltage transconductance, skewed flat-band voltage, and skewed threshold voltage, all of which are described in the Singer article.
It is possible to erase the effects of the damage caused by plasma etch by using a subsequent thermal annealing process. Annealing requires either a gradual or rapid heating of the wafer substrate in order to, inter alia, realign the interstitual defects caused by high energy ion bombardment. In many instances, rapid thermal anneal (RTA) requires temperatures exceeding, for example, 800.degree. C. or 900.degree. C. After a first metallization layer is deposited, and native oxides are sputter etch removed to allow contact with subsequent metallization layers, annealing can no longer be used to erase the deleterious effects of the sputter etch. After first metallization is placed, any subsequent annealing may melt or reflow the first metal causing problems such as poor step coverage, pin holes, hillocks etc. Thus, it is important that plasma etching after the first metallization be carefully controlled in order that damage does not occur since thermal anneal is not longer a suitable option for removing the damage at this stage of semiconductor process. It is important therefore that the plasma etch process be controlled in situ so that the source of wafer surface damage is minimized.
Referring now to the drawings, FIG. 1 illustrates an exemplary conventional rf sputter etching system 10 similar to that shown in U.S. Pat. No. 4,298,443 (herein incorporated by reference). System 10 includes an etching chamber 12 and, placed within chamber 12, is a holder 14. Holder 14 includes a plurality of flat surfaces or facets, each facet is designed to receive a plurality of wafers 16. Each wafer is held in place within aperatures 26 located within a front plate 18 by one or more clips or retainers 20. Front plate 18 constitutes an anode which can be fixedly secured to one facet of holder 14 via clamp 22. Retainers 20 firmly hold each wafer 16 in place against a cathode 24 during times in which plate 18 is secured to holder 14. Cathode 24 is adapted to receive rf power as well as sufficient cooling media necessary to electrically bias the surface of wafer 16 which is brought in electrical contact therewith, and also to cool the wafer during high energy ion bombardment.
Turning now to FIG. 2, a more detailed view of front plate 18 is illustrated. Plate 18 includes a plurality of aperatures 26, each of which sized to accommodate wafer 16. When placed upon holder 14, cathode 24 electrically abuts against the backside surface of wafer 16 to form a conductive path to the substrate of wafer 16. FIG. 2 illustrates four retainers 20 which clamp around the outer lip of wafer 16 as will be described further hereinbelow. Retainer 20 is made of a conductive material such as stainless steel, and is fixed to an insulating material placed at the base of retainer 20, between retainer 20 and front plate 18. The sides of retainer 20 are spaced a distance indicated by reference numeral 28 from a surrounding wall of front plate 18. As is well known in the art, front plate 18 is generally grounded and forms a portion of the system anode. Cathode 24 is therefore much smaller than the anode area and receives rf power from an rf exciter, phase shifter, amplifier, and matching network of common design. It is important that spacing 28 be maintained in an attempt to prevent or reduce shorting or "arcing" between anode (i.e., front plate 18) and wafer 16. If any arcing should occur, deleterious effects may present themselves during the sputter etch routine. It is postulated that arcing is generally caused by rapid accumulation of charge on the insulating surface of the wafer. After the charge builds to a critical value, it may then discharge or "arc" in a path of least resistance from retainer 20 to the closely spaced grounded plate 18. Arcing from wafer 16 to plate 18 is similar to the discharge of a capacitor. At a discharge current density of 0.1 ampere/cm.sup.2, a 1 .mu.m diameter area could receive a charge sufficient to cause the breakdown of the insulating layer (i.e., gate oxide breakdown) in less than 10 ns. A more detailed analysis of arcing and the postulated relationship between arcing and gate oxide breakdown will be described further with respect to FIG. 4 described hereinbelow.
Arcing is less likely to form in rf discharges because the field is maintained in one direction for less than one cycle, and reduces to zero twice in each cycle, making it more difficult for the arc to be sustained. Even so, arcing still may occur due to the accumulation (albeit charge accumulation must be more rapid) of charge such as ions on the self-biased insulator surface. Improper spacing between the wafer and anode only adds to the possibility of arcing. While it is important that the spacing not be too small, it is equally important that the spacing not be too large. Plate 18 must surround wafer 16 as close as possible in order to ensure the anode area is large and that the anode closely shields and confines the boundary area of the plasma completely around the working area of the wafer. Proper location of the "dark space" and plasma with respect to the target (or wafer) is well recognized as crucial to the functionality of the sputter etch chamber.
Referring now to FIG. 3, a more detailed view of plate 18 is shown. Specifically, a single aperature 26 is illustrated within plate 18 without a wafer retained therein. Aperature 26 is therefore of sufficient area to accommodate a wafer. The aperature can be of varying dimension to accommodate a four inch, six inch, eight inch, or larger diameter wafer. Plate 18 is made of a conductive material such as, for example, aluminum or stainless steel, and is preferably connected to a ground terminal associated with chamber 12.
At least one retainer, and preferably three or four retainers 20, are configured within grooves 30 (shown in partial cut-away section), wherein the walls of each groove 30 are spaced about the sides of a respective retainer 20. FIG. 3 illustrates a partially assembled portion of the backside surface of plate 18 without a wafer mounted within aperature 26. Retainer 20 includes an assembly having one end of retainer 20 or base 32 fixedly secured to a ledge portion of plate 18 by a screw 34. A complete description of the operating principles of retainer 20 and the composition of various materials used in retainer 20 are described in U.S. Pat. No. 4,473,455 (herein incorporated by reference). It is understood, when referencing Patent '455, that an inwardly projecting lip 36 is retained over the working surface of a semiconductor wafer, and that planar surface 38 of lip 36 abuts against the working surface.
After being loaded with wafers, plate 18 can be manually or automatically carried to the reaction chamber of system 10 for mounting to one of the facets containing cathode elements 24. The attributes of loading a wafer into an aperature 26 is schematically illustrated and described in an exemplary plasma etch chamber shown in U.S. Pat. No. 4,473,455. It is understood, however, that the retainer mechanism and etch chamber shown in Patents '443 and '455 are presented for exemplary purposes only.
Referring now to FIG. 4, a cross-sectional view of a loaded wafer 16 within plate 18 is shown. In particular, wafer 16 can be clamped or retained against the upper surface of cathode 22 by the protruding member or lip 36 of retainer 20. After processing, wafer 16 held in position within plate 18, can be easily removed. This is done by moving the associated spring elements of each retainer 20 toward the front side of plate 18 while engaging the backside of wafer 16 with a standard vacuum chuck. In such a way, the wafer can then be easily removed from its mounted position via the backside of plate 18.
The arcing phenomena described above generally occurs by the accumulation of charge on the insulating surface of wafer 16, and the transferral of that charge to and from grounded plate 18. Specifically, charge accumulates in the insulating regions, or contact windows, formed within areas 40 void of first metallization layer 42. Accumulation of charge can present itself, for example, as negative charge and, after a suitable accumulation has occurred, the charge may discharge through underlying dielectric layer 44, as shown. Dielectric layer 44 is an insulative material such as an oxide or spin-on glass (e.g., BPSG) well known in the art. Dielectric layer 44 is generally reduced or thinned during etch at select areas in order to allow contact to be made during the deposition of second metallization layer (not shown). The areas being thinned or removed over gate regions may cause significant electric field in those gate areas. It is well known that electric field, E, described by Coulomb's law and Gauss's law is more intense, i.e., has a greater force per unit charge in areas of thin insulative oxide such as gate oxide as described by Cheng, D., "Field and Wave Electromagnetics," Addison-Wesley Publ. Co., 1983, pp. 1-128, electromagnetic force energy between two points 1 and 2 can be expressed as follows: EQU F.sub.12 =a.sub.R12 kq.sub.1 q.sub.2 /(R.sub.12).sup.2,
where, F.sub.12 is the vector force exerted by q.sub.1 and q.sub.2, q.sub.1 and q.sub.2 is the electronic charge 1.6.times.10-19 Coulombs, a.sub.R12 is a unit vector in the direction from q.sub.1 to q.sub.2, R.sub.12 is the distance between charges q.sub.1 and q.sub.2, and k is the well known proportionality constant of silicon dioxide and silicon. The electric field intensity, E, can then be expressed as the force per unit charge or F.sub.12 /q within the semiconductor, whereby electric field is as follows: EQU E=a.sub.R12 q/4.pi..epsilon..sub.o R.sub.12.sup.2, or E=Q/C*L,
where, Q is the charge on the gate capacitor plate, .epsilon..sub.o is the well known permittivity of a dielectric medium (e.g., gate oxide 46), C is the gate capacitance, and L is the distance between opposite charge. It is important to note that E field is inversely proportional to the thinnest insulative region or gate oxide region due to the well known fact that the gate oxide is much thinner than the field oxide or glass regions.
Gate oxide breakdown associated with arcing generally occurs by the attractive forces of charges q.sub.1 and q.sub.2, where charges q.sub.1 and q.sub.2 are of opposite sign. Charges being attracted to one another across gate oxide 46 during etch pre-second metallization causes the gate concentration underneath the gate oxide, i.e. within the gate channel region 48, to sweep charges therefrom, resulting in a lower than optimal concentration of majority carriers. Thus, the charge within the channel region is attracted to and responds to a charge upon the gate as shown in FIG. 4. It is postulated that the attraction of charges may degrade the gate oxide if the amount of charge exceeds a critical level. Once a threshold amount of charge is allowed to accumulate, gate oxide breakdown may occur. Furthermore, lowering of concentration resulting from charge transferral within the channel region may skew the threshold voltage and flat-band voltage of the active device.
The mobility of the charge within substrate 50 and between channel region and grounded plate 18 adds to the electric field present within the gate oxide and compounds the problems described above. Transferral of charge from the substrate to plate 18 via retainer 20 only occurs when there is an arcing between plate 18 and retainer 20 in the low resistive path of spacing 28.
In order to reduce gate oxide breakdown or performance skews associated with charge concentration variability of the channel region, it is necessary to reduce the amount of charge underneath gate oxide 46. It has been presently determined that gate oxide damage and associated performance skews are primarily associated with p-channel transistors. The n-channel transistors placed within p-wells do not exhibit significant gate oxide breakdown after many production wafers were tested over a period of months. The n-channel test transistors exhibited a high degree of affinity toward gate oxide breakdown test voltages, however, the p-channel test transistors did not. As such, significant reduction in yield occurs on many devices incorporating CMOS process or any device having a p-channel transistor. It is postulated that the reason why n-channel transistors do not exhibit the problem is due to the depletion region formed between the p-well and underlying n-type substrate. The depletion region substantially prevents migration of charge to and from the n-channel gate oxide. The depletion region provides a barrier against migration of charges through the substrate from and to grounded plate 18. Instead of entering the n-channel active areas, it is assumed that the charge predominately migrates toward the p-channel regions instead, thereby causing deleterious effects therein. Repeated applications of high field inversion weakens the insulating properties of the gate oxide. If a large quantity of charge is present in the oxide or at the oxide/silicon interface, the effect will accelerate the breakdown due to lower field resistance.
Although wafer retainers, such as those shown in FIGS. 1-4, greatly enhance the throughput of plasma etching associated with rf sputtering, retainers 20 and their close spacing to anodes 18 can allow arcing and significant damage to the surface being etched. Due to the nature of sputter etching and associated electric field, any charge accumulation upon the insulating surface can cause arcing and problems of charge transferral described above. It is important when designing a sputter etch system, that the arcing phenomena be controlled or substantially reduced. It is therefore imperative that a sputter etch system be designed, or a wafer placed within the system be designed such that charge transferral arcing is minimized. The solution chosen must be cost effect and capable of being retrofitted to exiting sputter etch chambers. Still further, it might also be advantageous that modifications be made to the wafer instead of the chamber provided modification can be easily achieved without additional wafer processing steps and/or masks.